1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly to a phase detecting circuit that compares and detects phases of data and a clock and a clock generating apparatus including the same.
2. Related Art
A conventional semiconductor integrated circuit controls operations of individual regions of a circuit using a clock to increase the operational speed. In this regard, the semiconductor integrated circuit includes a clock generating apparatus such as a DLL (delay locked loop) circuit to compensate for timing delays associated with the external clock, thereby generating an internal clock. Thus, input or output data can be synchronized with the internal clock. Further, conventional semiconductor integrated circuits that operate at high speed may include a PLL (phase locked loop) circuit instead of the DLL circuit as the clock generating apparatus.
Both a DLL circuit and a PLL circuit basically include a phase detecting circuit. The phase detecting circuit of the DLL circuit compares and detects a phase of a reference clock input through a clock input buffer and a phase of a feedback clock output from a replica delay unit that performs modeling on a delayed time for transferring the output clock of a delay line to a data output buffer. The phase difference information detected from the phase detecting circuit is used to control the delay applied to the reference clock by the delay line. The PLL circuit also detects the phase difference of an input clock and an output clock, output from a voltage control oscillator, and controls the operation of a charge pump according to the detected result.
As described above, the phase detecting circuit performs an important function for determining a phase of a clock generated by the clock generating apparatus. However, recently, the operation speed of conventional semiconductor integrated circuits is increasing, and thus the frequency of the clock becomes much higher. Therefore, in conventional semiconductor integrated circuits that use a high frequency clock, the timing margin between the clock and the data is decreased since the time that is allocated to an input/output operation of a bit of data becomes shorter, which lowers the stability of data input/output operation. However, even though the stability is lowered due to the high speed operation, a conventional clock generating apparatus is not provided with a phase detecting circuit that is capable of detecting the timing of data and clock. As a result, the clock generating apparatus can not do anything when an error occurs during data input/output at high speeds. This can prevent the high speed semiconductor integrated circuit from being realized.